1. Field of the Invention
The present disclosure relates to a semiconductor device and a method of manufacturing the same. Particularly, the present disclosure relates to a technology which is effective when applied to a semiconductor device comprised of a power semiconductor switching device using a wide-gap semiconductor and to a method of manufacturing the same.
2. Description of the Related Art
In recent years, in view of such problems as global warming and anxiety about the supply of fossil fuels, attention has been paid to power electronics as a technology for promoting effective use of energy. Power electronics apparatuses are in charge of conversion and control of electric power, and there is a demand for enhancement of the performance of power semiconductor devices constituting a key to the power electronics apparatuses.
For power semiconductor devices, silicon (Si) substrates have long been used. With respect to Si power semiconductor devices, improvements for achieving a lower loss and higher performance have hitherto been made. As a result, the device performances of them have been approaching theoretical limits determined by the properties of the Si material, and, therefore, it has come to be difficult to achieve further enhancement of the performances in the future.
Under such circumstances, researches of low-loss power semiconductor devices using silicon carbide (SiC) or gallium nitride (GaN) have been made energetically. Silicon carbide (SiC) and gallium nitride (GaN) are higher than silicon (Si) in dielectric breakdown field intensity by about one order of magnitude, which enables a thinner drift layer. Therefore, the power semiconductor devices using the wide-gap semiconductor can achieve a lower ON resistance, and hence a lower loss, as compared with the Si power semiconductors.
As an example of power metal-oxide-semiconductor field-effect-transistor (MOSFET) conventionally used, a vertical double diffused MOS (DMOS) FET will be described below.
FIG. 1 is a top plan view of a typical DMOSFET semiconductor chip. A terminal end region 1001 is provided in an outer peripheral portion of the semiconductor chip. An active region 1002 and a gate pad region 1003 are provided on the inside of the terminal end region 1001. In the active region 1002, a multiplicity of unit cells constituting the MOSFET structure are regularly arranged.
FIG. 2 is a major part sectional view of a unit cell of a typical vertical DMOSFET structure. On a major surface of an n+-type SiC substrate 101 is provided an epitaxial layer 102 also composed of SiC, and a gate insulating film 221 and a gate electrode 222 are formed over the epitaxial layer 102. The front surface and side surfaces of the gate electrode 222 are covered with an interlayer insulating film 231. A source electrode 232 is formed in contact with the front surface of the epitaxial layer 102, in a source contact region 230 opened in the interlayer insulating film 231. On the back surface of the SiC substrate 101 is provided a drain electrode 103.
A p-type body region 201 is formed in the vicinity of the front surface of the epitaxial layer 102. An n-type source region 211 and a p+-type body contact region 202 containing a p-type impurity at a higher concentration than the p-type body region 201 are formed in the inside of the p-type body region 201. The source electrode 232 is formed in contact with, and in electrical connection to, the front surfaces of the n-type source region 211 and the p+-type body contact region 202. Therefore, the n-type source region 211 and the p+-type body contact region 202 are electrically short-circuited through the source electrode 232.
When a positive voltage is impressed on the gate electrode 222, a channel region is formed in that portion of the p-type body region 201 which is contacted by the gate insulating film 221 on the front surface side, and electrons flow from the n-type source region 211 toward the drain electrode 103 through the channel. Thus, a switching operation is performed by impressing a voltage on the gate electrode 222. A plurality of the unit cells are regularly and densely arranged in the active region, while sharing the source electrode 232, and they are connected in parallel on an electrical basis. By increasing the number of the unit cells connected in parallel, or the number of the unit cells laid over the active region, and enlarging the width of the channel regions arranged in the active region, a reduction in the resistance of the MOSFET chip as a whole can be realized.
FIGS. 3A and 3B show an example of top view layout of the unit cells arranged in the active region. Typically, the layouts shown in FIGS. 3A and 3B are used. In FIGS. 3A and 3B, there are shown, in top plan view, the n-type source regions 211, the channel regions at the front surface of the p-type body regions 201, the p+-type body contact regions 202, and the source contact regions 230, which are formed over the front surface of the epitaxial layer 102 of the DMOSFET structure.
The unit cell 1011 in FIG. 3A has an elongated belt-like shape, and the channel region is formed along the lengthwise direction of the belt. The sectional structure of the unit cell 1011 shown in FIG. 2 depicts the section along a cutting plane line X-X′ of FIG. 3A.
The unit cell in FIG. 3B has a tetragonal shape, and the channel region is formed along the four edges of the tetragon. The sectional structure of the unit cell shown in FIG. 2 depicts the section along a cutting plane line X-X′ and a cutting plane line Y-Y′ of FIG. 3B. In the tetragonal cells, the length of the channel regions arranged in the active region can be enlarged as compared to the belt-shaped cells, so that the tetragonal cell is advantageous from the viewpoint of lowering of resistance in a conduction state.